The present invention relates to a memory device, and in particular, to a memory device suitable for a graphic memory to be utilized in high-speed image processing.
The prior art technique will be described by referring to graphic processing depicted as an example in FIGS. 1-2. For example, the system of FIG. 1 comprises a graphic area M1 having a one-to-one correspondence with a cathode ray tube (CRT) screen, a store area M2 storing graphic data to be combined, and a modify section FC for combining the data in the graphic area M1 with the data in the store area M2. In FIG. 2, a processing flowchart includes a processing step S1 for reading data from the graphic area M1, a processing step S2 for reading data from the store area M2, a processing step S3 for combining the data read from the graphic area M1 and the data read from the store area M2, and a processing step S4 for writing the composite data generated in the step S3 in the graphic area M1.
In the graphic processing example, the processing step S3 of FIG. 2 performs a logical OR operation only to combine the data of the graphic area M1 with that of the store area M2.
On the other hand, the graphic area M1 to be subjected to the graphic processing must have a large memory capacity ranging from 100 kilobytes to several megabytes in ordinary cases. Consequently, in a series of graphic processing steps as shown in FIG. 2, the number of processing iterations to be executed is on the order of 10.sup.6 or greater even if the processing is conducted on each byte one at a time.
Similarly referring to FIGS. 2-3, graphic processing will be described in which the areas M1 and M2 store multivalued data such as color data for which a pixel is represented by the use of a plurality of bits.
Referring now to FIG. 3, a graphic processing arrangement comprises a memory area M1 for storing original multivalued graphic data and a memory area M2 containing multivalued graphic data to be combined therewith.
For the processing of multivalued graphic data shown in FIG. 3, addition is adopted as the operation to ordinarily generate composite graphic data. As a result, the values of data in the overlapped portion become larger, and hence a thicker picture is displayed as indicated by the crosshatching. In this case, the memory area must have a large memory capacity. The number of iterations of processing from the step S1 to the step S4 becomes on the order of 10.sup.6 or greater, as depicted in FIG. 2. Due to the large iteration count, most of the graphic data processing time is occupied by the processing time to be elapsed to process the loop of FIG. 2. In graphic data processing, therefore, the period of time utilized for the memory access becomes greater than the time elapsed for the data processing. Among the steps S1-S4 of FIG. 2, three steps S1, S2, and S4 are associated with the memory access. As described above, in such processing as graphic data processing in which memory having a large capacity is accessed, even if the operation speed is improved, the memory access time becomes a bottleneck of the processing, which restricts the processing speed and does not permit improving the effective processing speed of the graphic data processing system.
In the prior art examples, the following disadvantages take place.
(1) In the graphic processing as shown by use of the flowchart of FIG. 2, most of the processing is occupied by the steps S1, S2, and S4 which use a bus for memory read/write operations, consequently, the bus utilization ratio is increased and a higher load is imposed on the bus.
(2) The graphic processing time is further increased, for example, because the bus has a low transfer speed, or the overhead becomes greater due to the operation such as the bus control to dedicatedly allocate the bus to CRT display operation and to memory access.
(3) Moreover, although the flowchart of FIG. 2 includes only four static processing steps, a quite large volume of data must be processed as described before. volume of data must be processed as described before. That is, the number of dynamic processing steps which may elapse the effective processing time becomes very large, and hence a considerably long processing time is necessary.
Consequently, it is desirable to implement a graphic processing by use of a lower number of processing steps.
A memory circuit for executing the processing described above is found in the Japanese Patent Unexamined Publication No. 55-129387, for example.
Recent enhanced resolution of graphic display units is now demanding a large-capacity memory for use as a frame buffer for holding display information. In displaying a frame of graphic data, a large number of access operations to a capacious frame buffer take place, and therefore high-speed memory read/write operations are required. A conventional method for coping with this requirement is the distribution of processings.
An example of the distributed process is to carry out part of the process with a frame buffer. FIG. 26 shows, as an example, the arrangement of the frame buffer memory circuit, used in the method. The circuit includes an operation unit 1, a memory 2, an operational function control register 23, and a write mask register 26. The frame buffer writes data in bit units regardless of the word length of the memory device. On this account, the frame buffer writing process necessitates to implement operation and writing both in bit units. In the example of FIG. 26, bit operation is implemented by the operation unit 1 and operational function control register 23, while bit writing is implemented by the mask register 6 only to bits effective for writing. This frame buffer is designed to implement the memory read-modify-write operation in the write cycle for data D from the data processor, eliminating the need for the reading of data D0 out of the memory, which the usual memory necessitates in such operation, whereby speedup of the frame buffer operation is made possible.
FIG. 27 shows another example of distributed processing which is applied to a graphic display system consisting of two data processors 20 and 20' linked through a common bus 21 with a frame buffer memory 9". The frame buffer memory 9" is divided into two areas a and b which are operated for display by the data processors 20 and 20', respectively. FIG. 28 shows an example of a display made by this graphic system. The content of the frame buffer memory 9" is displayed on the CRT screen, which is divided into upper and lower sections in correspondence with the divided memory areas a and b as shown in FIG. 28. When it is intended to set up the memory 9" for displaying a circle, for example, the data processor 20 produces an arc .alpha..alpha.'.alpha." and the data processor 20' produces a remaining arc .beta..beta.'.beta." concurrently. The circular display process falls into two major processings of calculating the coordinates of the circle and writing the result into the frame buffer. In case the calculation process takes a longer time than the writing process, the use of the two processors 20 and 20' for the process is effective for the speedup of display. If, on the other hand, the writing process takes a longer time, the two processors conflict over the access to the frame buffer memory 9", resulting in a limited effectiveness of the dual processor system. The recent advanced LSI technology has significantly reduced the computation time of data processors relative to the memory write access time, which fosters the use of a frame buffer memory requiring less access operations such as one 9' shown in FIG. 26.
In application of the frame buffer memory 9' shown in FIG. 26 to the display system shown in FIG. 27, when both processors share in the same display process as shown in FIG. 28, the memory modification function is consistent for both processors and no problem will arise. In another case, however, if one processor draws graphic display a' and another processor draws character display b' as shown in FIG. 29, the system is no longer uneventful. In general, different kinds of display are accompanied by different memory modification operations, and if two processors make access to the frame buffer memory alternately, the setting for the modification operation and the read-modify-write operation need to take place in each display process. Setting for modification operation is identical to memory access when seen from the processor, and such double memory access ruins the attempt of speedup.
A conceivable scheme for reducing the number of computational settings is the memory access control in which one processor makes access to the frame buffer several times and then hands over the access right to another processor, instead of the alternate memory access control. However, this method requires additional time for the process of handing over the access right between the processors as compared with the display process using a common memory modification function. Namely, the conventional scheme of sharing in the same process among more than one data processor as shown in FIG. 28 is recently shifting to the implementation of separate processes as shown in FIG. 29 with a plurality of data processors, as represented by the multi-window system, and the memory circuit is not designed in consideration of this regard.
An example of the frame buffer using the read-modify-write operation is disclosed, for example, in an article entitled "Designing a 1280-by-1024 pixel graphic display frame buffer in a 64K RAM with nibble mode", Nikkei electronics, pp. 227-245, published on Aug. 27, 1984.